The ability to dynamically reconfigure hardware components has become critical to many computing systems. For example, to maintain optimal performance when the protocols, data rates, or physical medium attachment (PMA) layers change in communications systems, it is often essential to able to change more than just the software. Modern FPGA (field-programmable gate array) chips, which can be partially reconfigured at run time, are now in ubiquitous use to meet some of these needs in dedicated systems. For the rapidly advancing class of chips that have been developed to communicate with the brain, the ability to dynamically reconfigure the interface nodes has emerged as one of the most desirable features. A group of researchers from the Swiss Federal Institute of Technology has built a powerful new chip that can be rapidly adapted to changing conditions at its interface points. Furthermore, they have used their chip to show that the speed of communication between neurons is not independent from any computations a brain might be said to perform, but rather, it is an essential component of the computation itself.

     The chip developed by the Swiss group has some 11,011 electrodes packed into a CMOS chip with area less than 2x2mm. At 3,150 electrodes per square millimeter, that’s a higher density than anything we have seen to date. High-density chips with up to 65,000 stimulation sites have been manufactured before by other groups, but they generally have had little or no record (measure) ability. The key feature here is that the 126 signal-conditioned and amplified channels can be dynamically switched within a few milliseconds to any of the electrode sites in the grid, permitting multiresolutional access to neurons in its field on different spatial scales. The analog switch matrix which makes this possible consists of 13,00 static RAM cells which set the routing.

(extremetech)